Voltage regulator with soft-start circuit

ABSTRACT

A voltage regulator includes an operational amplifier, a transistor, a first resistor, a second resistor, an output voltage delaying circuit and a selecting circuit. The output voltage delaying circuit receives an output voltage and generates a delayed output voltage. A first input terminal of the selecting circuit receives a reference voltage. A second input terminal of the selecting circuit receives the delayed output voltage. An output terminal of the selecting circuit generates a control voltage to a first input terminal of the operational amplifier. If the reference voltage is larger than the delayed output voltage, the selecting circuit selects the delayed output voltage as the control voltage. If the reference voltage is smaller than the delayed output voltage, the selecting circuit selects the reference voltage as the control voltage.

This application claims the benefit of Taiwan Patent Application No.103136605, filed Oct. 23, 2014, the subject matter of which isincorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to a voltage regulator, and moreparticularly to a voltage regulator with a soft-start circuit.

BACKGROUND OF THE INVENTION

FIG. 1A is a schematic circuit diagram illustrating a conventionalvoltage regulator. FIG. 1B is a schematic timing waveform diagramillustrating associated signals processed by the conventional voltageregulator of FIG. 1A. The conventional voltage regulator 100 is a lowdropout voltage regulator (also referred as a LDO voltage regulator).The voltage regulator 100 comprises a reference voltage source, atransistor MP, an operational amplifier OP, a first resistor R1 and asecond resistor R2.

The operational amplifier OP is controlled according to an enablingsignal EN. A negative input terminal of the operational amplifier OPreceives a reference voltage Vref from the reference voltage source. Apositive input terminal of the operational amplifier OP receives afeedback voltage Vfb. An output terminal of the operational amplifier OPgenerates an error signal Ve. The gate terminal of the transistor MP isconnected to the output terminal of the operational amplifier OP. Thesource terminal of the transistor MP is connected to a power supplyvoltage Vcc. The drain terminal of the transistor MP is connected to anoutput terminal O of the voltage regulator 100. Moreover, a firstterminal of the first resistor R1 is connected to the drain terminal ofthe transistor MP, and a second terminal of the first resistor R1 isconnected to a node “a”. A first terminal of the second resistor R2 isconnected to the node “a”, and a second terminal of the second resistorR2 is connected to a ground voltage GND. Moreover, the feedback voltageVfb is outputted from the node “a”, and the node “a” is connected to thepositive input terminal of the operational amplifier OP.

The output terminal O of the voltage regulator 100 is connected to abulk capacitor Cb and a load 110. While the voltage regulator 100 isnormally operated, the transistor MP is controlled to generate an outputvoltage Vout according to the error signal Ve. Moreover, the outputvoltage Vout from the voltage regulator 100 is stabilized by the bulkcapacitor Cb. Consequently, the output terminal O of the voltageregulator 100 generates an output current Io to the load 110. Under thiscircumstance, the output voltage Vout may be expressed by the followingformula: Vout=(1+R1/R2)×Vref.

However, since the capacitance value of the bulk capacitor Cb is verylarge, the magnitude of the output current Io from the output terminal Oof the voltage regulator 100 is very large during the transient periodof starting up the voltage regulator 100. Consequently, the load 110 orthe transistor MP is possibly burnt out. Hereinafter, the relationshipsbetween the output voltage Vout and the output current Io of the voltageregulator 100 in some situations will be described in more details.

Please refer to FIG. 1B. At the time point t1, the voltage regulator 100is started. The high level state of the enabling signal EN indicatesthat the operational amplifier OP is in a normal working state.Consequently, the power supply voltage Vcc increases at a ramp rate.Obviously, during the period of increasing the power supply voltage Vcc,an overshoot phenomenon 120 of the output voltage Vout occurs and theoutput current Io is unstable.

At the time point t2, the power supply voltage Vcc is in the steadystate (e.g. 3.3V), and the enabling signal EN is switched from a lowlevel state to the high level state. Obviously, during the transientperiod of enabling the operational amplifier OP, an overshoot phenomenon122 of the output voltage Vout occurs and the output current Io is arush current. The rush current is larger than 2 A (2000 mA).Consequently, the load 110 or the transistor MP is possibly burnt out bythe output current Io.

At the time point t3, the enabling signal EN is in the high level state.Consequently, the power supply voltage Vcc quickly increases from 0V to3.3V. Obviously, during the transient period of starting up the voltageregulator 100, an overshoot phenomenon 124 of the output voltage Voutoccurs and the output current Io is a rush current. The rush current islarger than 0.5 A (500 mA). Consequently, the load 110 or the transistorMP is possibly burnt out by the output current Io.

Generally, during the transient period of starting up the voltageregulator 100, the voltage difference between the two input terminals ofthe operational amplifier OP is very large. Consequently, the magnitudeof the output current Io from the transistor MP is too large and theoutput voltage Vout has the overshoot phenomenon.

For avoiding the generation of the rush current during the transientperiod of starting up the voltage regulator 100, some soft-startcircuits have been disclosed in for example U.S. Pat. No. 8,704,506,U.S. Pat. No. 7,459,891, U.S. Pat. No. 7,619,397 and U.S. Pat. No.6,969,977. The soft-start circuit is applied to the voltage regulator toreduce the possibility of generating the rush current during thetransient period of starting up the voltage regulator.

SUMMARY OF THE INVENTION

The present invention provides a voltage regulator with a soft-startcircuit. The soft-start circuit has a simple circuitry configuration andis capable of effectively avoiding the rush current and the overshootphenomenon of the output voltage.

An embodiment of the present invention provides a voltage regulator. Thevoltage regulator includes an operational amplifier, a transistor, afirst resistor, a second resistor, an output voltage delaying circuitand a selecting circuit. A first input terminal of the operationalamplifier receives a control voltage. A second input terminal of theoperational amplifier receives a feedback voltage. An output terminal ofthe operational amplifier generates an error signal. A gate terminal ofthe transistor is connected to the output terminal of the operationalamplifier and receives the error signal. A first terminal of thetransistor receives a power supply voltage. A second terminal of thetransistor is connected to an output terminal of the voltage regulator.The output terminal of the voltage regulator generates an outputvoltage. A first terminal of the first resistor is connected to theoutput terminal of the voltage regulator. A second terminal of the firstresistor is connected to the second input terminal of the operationalamplifier. A first terminal of the second resistor is connected to thesecond terminal of the first resistor and generates the feedbackvoltage. A second terminal of the second resistor is connected to aground voltage. The output voltage delaying circuit is connected to theoutput terminal of the voltage regulator. The output voltage delayingcircuit receives the output voltage and generates a delayed outputvoltage. A first input terminal of the selecting circuit receives areference voltage. A second input terminal of the selecting circuitreceives the delayed output voltage. An output terminal of the selectingcircuit generates the control voltage to the first input terminal of theoperational amplifier. If the reference voltage is larger than thedelayed output voltage, the selecting circuit selects the delayed outputvoltage as the control voltage. If the reference voltage is smaller thanthe delayed output voltage, the selecting circuit selects the referencevoltage as the control voltage.

Numerous objects, features and advantages of the present invention willbe readily apparent upon a reading of the following detailed descriptionof embodiments of the present invention when taken in conjunction withthe accompanying drawings. However, the drawings employed herein are forthe purpose of descriptions and should not be regarded as limiting.

BRIEF DESCRIPTION OF THE DRAWINGS

The above objects and advantages of the present invention will becomemore readily apparent to those ordinarily skilled in the art afterreviewing the following detailed description and accompanying drawings,in which:

FIG. 1A (prior art) is a schematic circuit diagram illustrating aconventional voltage regulator;

FIG. 1B (prior art) is a schematic timing waveform diagram illustratingassociated signals processed by the conventional voltage regulator ofFIG. 1A;

FIG. 2A is a schematic circuit diagram illustrating a voltage regulatoraccording to an embodiment of the present invention;

FIG. 2B is a schematic timing waveform diagram illustrating associatedsignals processed by the voltage regulator of FIG. 2A;

FIGS. 3A and 3B schematically illustrate two examples of the outputvoltage delaying circuit used in the voltage regulator of the presentinvention; and

FIGS. 4A and 4B schematically illustrate two examples of the selectingcircuit used in the voltage regulator of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 2A is a schematic circuit diagram illustrating a voltage regulatoraccording to an embodiment of the present invention. FIG. 2B is aschematic timing waveform diagram illustrating associated signalsprocessed by the voltage regulator of FIG. 2A. The voltage regulator 200comprises a reference voltage source, a selecting circuit 210, atransistor MP, an operational amplifier OP, an output voltage delayingcircuit 220, a first resistor R1 and a second resistor R2. Moreover, asoft-start circuit is defined by the selecting circuit 210 and theoutput voltage delaying circuit 220 collaboratively.

In this embodiment, the two input terminals of the selecting circuit 210receive a reference voltage Vref from the reference voltage source and adelayed output voltage Vss from the output voltage delaying circuit 220.Moreover, a control voltage Vr is outputted from an output terminal ofthe selecting circuit 210. If the reference voltage Vref is larger thanthe delayed output voltage Vss, the selecting circuit 210 selects thedelayed output voltage Vss as the control voltage Vr. Whereas, if thereference voltage Vref is smaller than the delayed output voltage Vss,the selecting circuit 210 selects the reference voltage Vref as thecontrol voltage Vr.

The operational amplifier OP of the voltage regulator 200 is controlledaccording to an enabling signal EN. A negative input terminal of theoperational amplifier OP receives the control voltage Vr. A positiveinput terminal of the operational amplifier OP receives a feedbackvoltage Vfb. An output terminal of the operational amplifier OPgenerates an error signal Ve. The gate terminal of the transistor MP isconnected to the output terminal of the operational amplifier OP. Thesource terminal of the transistor MP is connected to a power supplyvoltage Vcc. The drain terminal of the transistor MP is connected to anoutput terminal O of the voltage regulator 200. Moreover, a firstterminal of the first resistor R1 is connected to the drain terminal ofthe transistor MP, and a second terminal of the first resistor R1 isconnected to a node “a”. A first terminal of the second resistor R2 isconnected to the node “a”, and a second terminal of the second resistorR2 is connected to a ground voltage GND. Moreover, the feedback voltageVfb is outputted from the node “a”, and the node “a” is connected to thepositive input terminal of the operational amplifier OP. Moreover, theoutput voltage delaying circuit 220 is connected between the outputterminal O of the voltage regulator 200 and the selecting circuit 210.The output voltage delaying circuit 220 may receive an output voltageVout from the output terminal O of the voltage regulator 200 andgenerate the delayed output voltage Vss to the selecting circuit 210.

The output terminal O of the voltage regulator 200 is connected to abulk capacitor Cb and a load 230. While the voltage regulator 100 isnormally operated, the transistor MP is controlled to generate theoutput voltage Vout according to the error signal Ve. Moreover, theoutput voltage Vout from the voltage regulator 200 is stabilized by thebulk capacitor Cb. Consequently, the output terminal O of the voltageregulator 200 generates an output current Io to the load 230. Under thiscircumstance, the output voltage Vout may be expressed by the followingformula:Vout=(1+R1/R2)×Vref.

In accordance with a feature of the present invention, during thetransient period of starting up the voltage regulator 200, the voltagedifference between the two input terminals of the operational amplifierOP is reduced according to the control voltage Vr from the soft-startcircuit. Consequently, the possibility of generating the overshootphenomenon of the output voltage Vout is minimized.

In other words, during the transient period of starting up the voltageregulator 200, the magnitudes of the output voltage Vout and thefeedback voltage Vfb are very small. Meanwhile, the selecting circuit210 selects the delayed output voltage Vss as the control voltage Vr,and the delayed output voltage Vss is inputted into the negative inputterminal of the operational amplifier OP. Consequently, the positiveinput terminal and the negative input terminal of the operationalamplifier OP receive the feedback voltage Vfb and the delayed outputvoltage Vss, respectively. Since the voltage difference between the twoinput terminals of the operational amplifier OP is smaller, theovershoot phenomenon of the output voltage Vout and the rush current canbe effectively inhibited.

Moreover, after the transient period of starting up the voltageregulator 200, if the delayed output voltage Vss is larger than thereference voltage Vref, the selecting circuit 210 selects the referencevoltage Vref as the control voltage Vr, and the reference voltage Vrefis inputted into the negative input terminal of the operationalamplifier OP. Since the positive input terminal and the negative inputterminal of the operational amplifier OP receive the feedback voltageVfb and the delayed output voltage Vss, respectively, the outputterminal O of the voltage regulator 200 can generate the stable outputvoltage Vout.

Please refer to FIG. 2B. At the time point t1, the voltage regulator 200is started. The high level state of the enabling signal EN indicatesthat the operational amplifier OP is in a normal working state.Consequently, the power supply voltage Vcc increases at a ramp rate.Obviously, during the period of increasing the power supply voltage Vcc,no overshoot phenomenon of the output voltage Vout occurs. Moreover, thepeak value of the output current Io is about 90 mA.

At the time point t2, the power supply voltage Vcc is in the steadystate (e.g. 3.3V), and the enabling signal EN is switched from a lowlevel state to the high level state. Obviously, during the transientperiod of enabling the operational amplifier OP, no overshoot phenomenonof the output voltage Vout occurs. Moreover, the peak value of theoutput current Io is about 90 mA.

At the time point t3, the enabling signal EN is in the high level state.Consequently, the power supply voltage Vcc quickly increases from 0V to3.3V. Obviously, during the transient period of starting up the voltageregulator 200, no overshoot phenomenon of the output voltage Voutoccurs. Moreover, the peak value of the output current Io is about 90mA.

From the above descriptions, the soft-start circuit is defined by theselecting circuit 210 and the output voltage delaying circuit 220collaboratively. During the transient period of starting up the voltageregulator 200, the soft-start circuit is capable of effectively reducingthe output current Io from the voltage regulator 200 and avoiding thegeneration of the overshoot phenomenon of the output voltage Vout.

FIGS. 3A and 3B schematically illustrate two examples of the outputvoltage delaying circuit used in the voltage regulator of the presentinvention.

As shown in FIG. 3A, the output voltage delaying circuit 220 comprises athird resistor R3 and a capacitor C1. A first terminal of the thirdresistor R3 receives the output voltage Vout. A second terminal of thethird resistor R3 is connected to a first terminal of the capacitor C1.A second terminal of the capacitor C1 is connected to the ground voltageGND. Moreover, the second terminal of the third resistor R3 generatesthe delayed output voltage Vss to the selecting circuit 210. In thisembodiment, the delayed time of the output voltage delaying circuit 220is determined according to the time constant of the RC circuit (i.e.R3×C1). If the delayed time is longer, the output voltage Vout increasesat a slower rate during the transient start-up period and thepossibility of generating the overshoot phenomenon of the output voltageVout decreases. On the other hand, if the delayed time is shorter, theoutput voltage Vout increases at a faster rate during the transientstart-up period and the possibility of generating the overshootphenomenon of the output voltage Vout increases.

As shown in FIG. 3B, the output voltage delaying circuit 220 comprises aunity gain buffer 222 and a capacitor C1. An input terminal of the unitygain buffer 222 receives the output voltage Vout. An output terminal ofthe unity gain buffer 222 is connected to a first terminal of thecapacitor C1. A second terminal of the capacitor C1 is connected to theground voltage GND. Moreover, an output terminal of the unity gainbuffer 222 generates the delayed output voltage Vss to the selectingcircuit 210. In this embodiment, the delayed time of the output voltagedelaying circuit 220 is determined according to the driving strength ofthe unity gain buffer 222. If the driving strength is weaker, the outputvoltage Vout increases at a slower rate during the transient start-upperiod and the possibility of generating the overshoot phenomenon of theoutput voltage Vout decreases. On the other hand, if the drivingstrength is stronger, the output voltage Vout increases at a faster rateduring the transient start-up period and the possibility of generatingthe overshoot phenomenon of the output voltage Vout increases. In thisembodiment, the unity gain buffer 222 is implemented by an operationalamplifier. In addition, the negative input terminal and the outputterminal of the operational amplifier are connected with each other.

FIGS. 4A and 4B schematically illustrate two examples of the selectingcircuit used in the voltage regulator of the present invention.

As shown in FIG. 4A, the selecting circuit 210 comprises a comparator212, a first switching element Msw1 and a second switching element Msw2.A positive input terminal of the comparator 212 receives the referencevoltage Vref. A negative input terminal of the comparator 212 receivesthe delayed output voltage Vss. An output terminal of the comparator 212generates a switching signal Csw. A control terminal of the firstswitching element Msw1 receives the switching signal Csw. A firstterminal of the first switching element Msw1 is connected to thepositive input terminal of the comparator 212. A control terminal of thesecond switching element Msw2 receives the switching signal Csw. A firstterminal of the second switching element Msw2 is connected to thenegative input terminal of the comparator 212. A second terminal of thesecond switching element Msw2 is connected to a second terminal of thefirst switching element Msw1. In this embodiment, the first switchingelement Msw1 is a P-type transistor, and the second switching elementMsw2 is an N-type transistor.

Obviously, if the reference voltage Vref is larger than the delayedoutput voltage Vss, the switching signal Csw is in a high level state.Under this circumstance, the second switching element Msw2 is in a closestate, and the first switching element Msw1 is in an open state.Consequently, the selecting circuit 210 selects the delayed outputvoltage Vss as the control voltage Vr. On the other hand, if thereference voltage Vref is smaller than the delayed output voltage Vss,the switching signal Csw is in a low level state. Under thiscircumstance, the first switching element Msw1 is in the close state,and the second switching element Msw2 is in the open state.Consequently, the selecting circuit 210 selects the reference voltageVref as the control voltage Vr.

As shown in FIG. 4B, the selecting circuit 210 comprises a comparator212, an inverter 214, a first transmission gate 216 and a secondtransmission gate 218. A positive input terminal of the comparator 212receives the reference voltage Vref. A negative input terminal of thecomparator 212 receives the delayed output voltage Vss. An outputterminal of the comparator 212 generates a switching signal Csw. Theinverter 214 receives the switching signal Csw and generates an invertedswitching signal Cswb. A first control terminal of the firsttransmission gate 216 receives the switching signal Csw, and a secondcontrol terminal of the first transmission gate 216 receives theinverted switching signal Cswb. A first terminal of the firsttransmission gate 216 is connected to the positive input terminal of thecomparator 212. A first control terminal of the second transmission gate218 receives the inverted switching signal Cswb, and a second controlterminal of the second transmission gate 218 receives the switchingsignal Csw. A first terminal of the second transmission gate 218 isconnected to the negative input terminal of the comparator 212. A secondterminal of the second transmission gate 218 is connected to a secondterminal of the first transmission gate 216.

Obviously, if the reference voltage Vref is larger than the delayedoutput voltage Vss, the switching signal Csw is in a high level stateand the inverted switching signal Cswb is in a low level state. Underthis circumstance, the second transmission gate 218 is in a close state,and the first transmission gate 216 is in an open state. Consequently,the selecting circuit 210 selects the delayed output voltage Vss as thecontrol voltage Vr. On the other hand, if the reference voltage Vref issmaller than the delayed output voltage Vss, the switching signal Csw isin the low level state and the inverted switching signal Cswb is in thehigh level state. Under this circumstance, the first transmission gate216 is in the close state, and the second transmission gate 218 in theopen state. Consequently, the selecting circuit 210 selects thereference voltage Vref as the control voltage Vr.

It is noted that numerous modifications and alterations of the selectingcircuit 210 may be made while retaining the teachings of the invention.For example, in some other embodiments, the positive input terminal ofthe comparator 212 receives the delayed output voltage Vss, the negativeinput terminal of the comparator 212 receives the reference voltageVref, and the output terminal of the comparator 212 generates theswitching signal Csw. Moreover, the connecting relationship between theswitching elements or the transmission gates may be modified whileachieving the function of the selecting circuit 210.

From the above descriptions, the present invention provides a voltageregulator with a soft-start circuit. The soft-start circuit is capableof effectively reducing the output current Io and avoiding thegeneration of the overshoot phenomenon of the output voltage Vout duringthe transient period of starting up the voltage regulator.

While the invention has been described in terms of what is presentlyconsidered to be the most practical and preferred embodiments, it is tobe understood that the invention needs not be limited to the disclosedembodiment. On the contrary, it is intended to cover variousmodifications and similar arrangements included within the spirit andscope of the appended claims which are to be accorded with the broadestinterpretation so as to encompass all such modifications and similarstructures.

What is claimed is:
 1. A voltage regulator, comprising: an operationalamplifier, wherein a first input terminal of the operational amplifierreceives a control voltage, a second input terminal of the operationalamplifier receives a feedback voltage, and an output terminal of theoperational amplifier generates an error signal; a transistor, wherein agate terminal of the transistor is connected to the output terminal ofthe operational amplifier and receives the error signal, a firstterminal of the transistor receives a power supply voltage, and a secondterminal of the transistor is connected to an output terminal of thevoltage regulator, wherein the output terminal of the voltage regulatorgenerates an output voltage; a first resistor, wherein a first terminalof the first resistor is connected to the output terminal of the voltageregulator, and a second terminal of the first resistor is connected tothe second input terminal of the operational amplifier; a secondresistor, wherein a first terminal of the second resistor is connectedto the second terminal of the first resistor and generates the feedbackvoltage, and a second terminal of the second resistor is connected to aground voltage; an output voltage delaying circuit connected to theoutput terminal of the voltage regulator, wherein the output voltagedelaying circuit receives the output voltage and generates a delayedoutput voltage; and a selecting circuit, wherein a first input terminalof the selecting circuit receives a reference voltage, a second inputterminal of the selecting circuit receives the delayed output voltage,and an output terminal of the selecting circuit generates the controlvoltage to the first input terminal of the operational amplifier,wherein if the reference voltage is larger than the delayed outputvoltage, the selecting circuit selects the delayed output voltage as thecontrol voltage, wherein if the reference voltage is smaller than thedelayed output voltage, the selecting circuit selects the referencevoltage as the control voltage.
 2. The voltage regulator as claimed inclaim 1, wherein the output terminal of the voltage regulator is furtherconnected to a bulk capacitor and a load.
 3. The voltage regulator asclaimed in claim 1, wherein the output voltage delaying circuitcomprises: a third resistor, wherein a first terminal of the thirdresistor is connected to the output terminal of the voltage regulatorand receives the output voltage; and a first capacitor, wherein a firstterminal of the first capacitor is connected to a second terminal of thethird resistor and generates the delayed output voltage, and a secondterminal of the first capacitor is connected to the ground voltage. 4.The voltage regulator as claimed in claim 1, wherein the output voltagedelaying circuit comprises: a unity gain buffer, wherein an inputterminal of the unity gain buffer is connected to the output terminal ofthe voltage regulator and receives the output voltage; and a firstcapacitor, wherein a first terminal of the first capacitor is connectedto an output terminal of the unity gain buffer and generates the delayedoutput voltage, and a second terminal of the first capacitor isconnected to the ground voltage.
 5. The voltage regulator as claimed inclaim 1, wherein the selecting circuit comprises: a comparator, whereina first input terminal of the comparator receives the reference voltage,a second input terminal of the comparator receives the delayed outputvoltage, and an output terminal of the comparator generates a switchingsignal; a first switching element, wherein a control terminal of thefirst switching element receives the switching signal, and a firstterminal of the first switching element is connected to the first inputterminal of the comparator and receives the reference voltage; and asecond switching element, wherein a control terminal of the secondswitching element receives the switching signal, a first terminal of thesecond switching element is connected to the second input terminal ofthe comparator and receives the delayed output voltage, and a secondterminal of the second switching element is connected to a secondterminal of the first switching element and generates the controlvoltage.
 6. The voltage regulator as claimed in claim 5, wherein if thereference voltage is larger than the delayed output voltage, the firstswitching element is in an open state and the second switching elementis in a close state, so that the selecting circuit selects the delayedoutput voltage as the control voltage, wherein if the reference voltageis smaller than the delayed output voltage, the first switching elementis in the close state and the second switching element is in the openstate, so that the selecting circuit selects the reference voltage asthe control voltage.
 7. The voltage regulator as claimed in claim 5,wherein the first switching element is a P-type transistor, and thesecond switching element is an N-type transistor.
 8. The voltageregulator as claimed in claim 1, wherein the selecting circuitcomprises: a comparator, wherein a first input terminal of thecomparator receives the reference voltage, a second input terminal ofthe comparator receives the delayed output voltage, and an outputterminal of the comparator generates a switching signal; an inverter,wherein an input terminal of the inverter receives the switching signal,and an output terminal of the inverter generates an inverted switchingsignal; a first transmission gate, wherein a first control terminal ofthe first transmission gate receives the switching signal, a secondcontrol terminal of the first transmission gate receives the invertedswitching signal, and a first terminal of the first transmission gate isconnected to the first input terminal of the comparator and receives thereference voltage; and a second transmission gate, wherein a firstcontrol terminal of the second transmission gate receives the invertedswitching signal, a second control terminal of the second transmissiongate receives the switching signal, a first terminal of the secondtransmission gate is connected to the second input terminal of thecomparator and receives the delayed output voltage, and a secondterminal of the second transmission gate is connected to a secondterminal of the first transmission gate and generates the controlsignal.
 9. The voltage regulator as claimed in claim 8, wherein if thereference voltage is larger than the delayed output voltage, the firsttransmission gate is in an open state and the second transmission gateis in a close state, so that the selecting circuit selects the delayedoutput voltage as the control voltage, wherein if the reference voltageis smaller than the delayed output voltage, the first transmission gateis in the close state and the second transmission gate is in the openstate, so that the selecting circuit selects the reference voltage asthe control voltage.
 10. The voltage regulator as claimed in claim 1,wherein the operational amplifier further has an enabling terminalreceiving an enabling signal, wherein the operational amplifier isoperated according to the enabling signal.